This relates to a MOS gate structure and a method for forming the gate. It is especially useful in high-k dielectric last technology and will be described in that context. However, it may also be used in other technologies.
In recent years, the continued progress in reducing the physical size of semiconductors has required a major change in the composition of the gate structure in a PMOS or NMOS transistor. In particular, the thickness of the silicon dioxide insulator became so small that quantum effects resulted in substantial leakage currents through the insulator. As a result, it became necessary to replace the silicon dioxide insulator and, with it, the polysilicon gate. The replacement structure was a metal gate with a high-k dielectric that greatly reduced the leakage current For further details, see M. T. Bohr, et al., “The High-k Solution”, IEEE Spectrum (October 2007); E. P. Gusev et al, “Advanced High-k Dielectric Stacks with PolySi and Metal Gates: Recent Progress and Current Challenges,” IBM J. Res. & Dev., Vol. 50, No. 4/5 (July/September 2006), both of which are incorporated herein in their entireties.
The use of a metal gate and high-k dielectric introduced other issues into the semiconductor device manufacturing process. Of particular importance, high temperature annealing operations performed after implanting operations such as those for forming LDD regions, sources and drains were not compatible with the metal gate and high-k dielectric structures. As a result, fabrication processes were developed and implemented in which the high-k dielectric and metal layer were the last elements to be formed in the process. Such fabrication processes are sometimes referred to as high-k dielectric last processes.
While the high-k dielectric last process has facilitated the implementation of the Semiconductor Roadmap at technology nodes of 65 nm and beyond, the constantly decreasing size of the MOS gate continues to produce challenges. For example, other types of current leakage such as that caused by drain induced barrier lowering (DIBL) remain a problem. And capacitance between the gate and the source/drain (gate-source/drain overlap capacitance (Cov)) interferes with efforts to increase the switching speed of the transistors in devices such as Field Programmable Gate Arrays (FPGA). There are also problems in the fabrication of the structures of the semiconductor devices. For example, as the length of the transistor gates gets smaller and smaller, the size of the holes made in the insulating layer to form the gates should also get smaller except that it becomes increasingly more difficult to fill those holes with gate metallization.